Dissertation Title: Design Automation Methods for Memory-based Reconfigurable Computing
Date: 2026/02/02 – 2026/02/02
Dissertation Title: Design Automation Methods for Memory-based Reconfigurable Computing
Speaker: Xingyue Qian, Ph.D. candidate at SJTU Global College
Time: February 2nd from 2:00-4:00 p.m., 2026 (Beijing Time)
Location: Room 414A, Longbin Building
Abstract
There are two types of methods to perform computation tasks, through hardware and through software. Many reconfigurable architectures are proposed to combine the strength of both methods. They have the high performance of the hardware methods and the flexibility of the software methods. In traditional computer system, memories are typically used for data storage. However, recent works show that they can also be used to preform reconfigurable computing in order to improve efficiency. In the dissertation study, the author focuses on the design automation methods for two types of memory-based reconfigurable architectures: compute with memory and logic-in-memory (LiM).
Compute with memory methods store the pre-computed results of frequently-used functions in a lookup table (LUT) and retrieve the result at runtime. For error-tolerant applications, approximate LUT architectures can trade accuracy for performance improvement. A recent work proposes Boolean decomposition-based approximate LUT that can support both continuous and non-continuous functions. However, its decomposition algorithm is greedy and its architecture is rigid. To address the issue, the author proposes HalpaLUT to improve the accuracy and power consumption for Boolean decomposition-based approximate LUT. The proposed method consists of a novel approximate decomposition algorithm and two flexible reconfigurable architectures. Compared to the state-of-the-art, the decomposition algorithm achieves 11.1% less error by using half runtime, and the two reconfigurable architectures have 10.4% less error using 19.2% less energy and 23.0% less error using the same amount of energy, respectively.
LiM architectures can perform primitive logic operations, such as XOR and majority, within memory arrays to avoid the costly data transfer between processor and memory. To efficiently use a LiM architecture to compute the target function, a compiler is needed that consists of two steps: logic synthesis, which transforms the function into a netlist comprising the supported operations, and scheduling, which generates the instructions to compute the operations. On the one hand, it is important to build a high-performance scheduler. In the ideal case, the target function is computed in a single array to achieve low energy consumption and high parallelism. To enable functions with large netlists to be computed within a single array with limited size, the author proposes FISIM to reduce memory footprint. The scheduler consists of a scheduling-friendly bipartition algorithm and a novel fast optimal scheduler. Compared to the best state-of-the-art heuristic method, FISIM reduces the memory footprint by 25.5% under the same runtime. When multiple arrays must be used, the author develops MASIM to reduce the energy-consuming cross-array data copy instructions. It consists of a priority-based scheduling algorithm and an iterative improvement process. Compared to the best existing scheduler, MASIM reduces the number of copy instructions by 63.2% on average, leading to a 28.0% reduction in energy. On the other hand, most compilers perform logic synthesis and scheduling in serial just once to obtain a design with suboptimal performance. The recent reinforcement learning-based solution attempts to improve the baseline design, but its efficiency is too low to achieve a good result. To overcome these limitations, the author builds HICIM to effectively explore the design space. The compiler adopts an iterative flow with tightly coupling of logic synthesis and scheduling, which can identify better designs with an average 15.6% reduction in energy-delay product.
To sum up, the proposed design automation methods can automatically transform the computation task into high-quality hardware design that can be implemented on the memory-based reconfigurable architectures with good end-to-end performance.
Biography
Xingyue Qian received the B.S. degree in Electrical and Computer Engineering from the Global College, Shanghai Jiao Tong University, Shanghai, China, in 2020. She is currently pursuing the Ph.D. degree in Electronic Science and Technology at the same institute. Her current research includes high-level synthesis, approximate computing, and in-memory computing.